深入了解iommu系列最终章：Interrupt Posting 机制和工作原理

struct pi_desc {
        u32 pir[8];     /* Posted interrupt requested */
        union {
                struct {
                                /* bit 256 - Outstanding Notification */
                        u16     on      : 1,
                                /* bit 257 - Suppress Notification */
                                sn      : 1,
                                /* bit 271:258 - Reserved */
                                rsvd_1  : 14;
                                /* bit 279:272 - Notification Vector */
                        u8      nv;
                                /* bit 287:280 - Reserved */
                        u8      rsvd_2;
                                /* bit 319:288 - Notification Destination */
                        u32     ndst;
                };
                u64 control;
        };
        u32 rsvd[6];
} __aligned(64);

irqfd->consumer.add_producer = kvm_arch_irq_bypass_add_producer

                /*
                 * VT-d PI cannot support posting multicast/broadcast
                 * interrupts to a vCPU, we still use interrupt remapping
                 * for these kind of interrupts.
                 *
                 * For lowest-priority interrupts, we only support
                 * those with single CPU as the destination, e.g. user
                 * configures the interrupts via /proc/irq or uses
                 * irqbalance to make the interrupts single-CPU.
                 *
                 * We will support full lowest-priority interrupt later.
                 */

                kvm_set_msi_irq(kvm, e, &irq);
                if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
                        /*
                         * Make sure the IRTE is in remapped mode if
                         * we don't handle it in posted mode.
                         */
                        ret = irq_set_vcpu_affinity(host_irq, NULL);
                        if (ret < 0) {
                                printk(KERN_INFO
                                   "failed to back to remapped mode, irq: %u\n",
                                   host_irq);
                                goto out;
                        }

                        continue;
                }

                vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
                vcpu_info.vector = irq.vector;

                trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
                                vcpu_info.vector, vcpu_info.pi_desc_addr, set);

                if (set)
                        ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
                else
                        ret = irq_set_vcpu_affinity(host_irq, NULL);

chip->irq_set_vcpu_affinity(data, vcpu_info)

static int intel_ir_set_vcpu_affinity(struct irq_data *data, void *info)
{
        struct intel_ir_data *ir_data = data->chip_data;
        struct vcpu_data *vcpu_pi_info = info;

        /* stop posting interrupts, back to remapping mode */
        if (!vcpu_pi_info) {
                modify_irte(&ir_data->irq_2_iommu, &ir_data->irte_entry);
        } else {
                struct irte irte_pi;

                /*
                 * We are not caching the posted interrupt entry. We
                 * copy the data from the remapped entry and modify
                 * the fields which are relevant for posted mode. The
                 * cached remapped entry is used for switching back to
                 * remapped mode.
                 */
                memset(&irte_pi, 0, sizeof(irte_pi));
                dmar_copy_shared_irte(&irte_pi, &ir_data->irte_entry);

                /* Update the posted mode fields */
                irte_pi.p_pst = 1;
                irte_pi.p_urgent = 0;
                irte_pi.p_vector = vcpu_pi_info->vector;
                irte_pi.pda_l = (vcpu_pi_info->pi_desc_addr >>
                                (32 - PDA_LOW_BIT)) & ~(-1UL << PDA_LOW_BIT);
                irte_pi.pda_h = (vcpu_pi_info->pi_desc_addr >> 32) &
                                ~(-1UL << PDA_HIGH_BIT);

                modify_irte(&ir_data->irq_2_iommu, &irte_pi);
        }

        return 0;
}

......
        /* The full case.  */
        do {
                old.control = new.control = pi_desc->control;

                dest = cpu_physical_id(cpu);

                if (x2apic_enabled())
                        new.ndst = dest;
                else
                        new.ndst = (dest << 8) & 0xFF00;

                new.sn = 0;
        } while (cmpxchg64(&pi_desc->control, old.control,
                           new.control) != old.control);
......

 local_irq_disable();
 if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
                vcpu->pre_pcpu = vcpu->cpu;
                spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
                list_add_tail(&vcpu->blocked_vcpu_list,
                              &per_cpu(blocked_vcpu_on_cpu,
                                       vcpu->pre_pcpu));
                spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
        }

        do {
                old.control = new.control = pi_desc->control;

                WARN((pi_desc->sn == 1),
                     "Warning: SN field of posted-interrupts "
                     "is set before blocking\n");

                /*
                 * Since vCPU can be preempted during this process,
                 * vcpu->cpu could be different with pre_pcpu, we
                 * need to set pre_pcpu as the destination of wakeup
                 * notification event, then we can find the right vCPU
                 * to wakeup in wakeup handler if interrupts happen
                 * when the vCPU is in blocked state.
                 */
                dest = cpu_physical_id(vcpu->pre_pcpu);

                if (x2apic_enabled())
                        new.ndst = dest;
                else
                        new.ndst = (dest << 8) & 0xFF00;

                /* set 'NV' to 'wakeup vector' */
                new.nv = POSTED_INTR_WAKEUP_VECTOR;
        } while (cmpxchg64(&pi_desc->control, old.control,
                           new.control) != old.control);

     /* We should not block the vCPU if an interrupt is posted for it.  */
        if (pi_test_on(pi_desc) == 1)
                __pi_post_block(vcpu);
        local_irq_enable();
        return (vcpu->pre_pcpu == -1)

static void __pi_post_block(struct kvm_vcpu *vcpu)
{
        struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
        struct pi_desc old, new;
        unsigned int dest;

        do {
                old.control = new.control = pi_desc->control;
                WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
                     "Wakeup handler not enabled while the VCPU is blocked\n");

                dest = cpu_physical_id(vcpu->cpu);

                if (x2apic_enabled())
                        new.ndst = dest;
                else
                        new.ndst = (dest << 8) & 0xFF00;

                /* set 'NV' to 'notification vector' */
                new.nv = POSTED_INTR_VECTOR;
        } while (cmpxchg64(&pi_desc->control, old.control,
                           new.control) != old.control);

        if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
                spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
                list_del(&vcpu->blocked_vcpu_list);
                spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
                vcpu->pre_pcpu = -1;
        }
}

irqfd_inject->kvm_set_irq->
                kvm_set_msi->kvm_irq_delivery_to_apic

static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
{
        struct vcpu_vmx *vmx = to_vmx(vcpu);
        int r;

        r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
        if (!r)
                return;

        if (pi_test_and_set_pir(vector, vmx->pi_desc))
                return;
        /* If a previous notification has sent the IPI, nothing to do.  */
        if (pi_test_and_set_on(vmx->pi_desc))
                return;

        if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
                kvm_vcpu_kick(vcpu);
}

static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
                                                     bool nested)
{
#ifdef CONFIG_SMP
        int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;

        if (vcpu->mode == IN_GUEST_MODE) {
                /*
                 * The vector of interrupt to be delivered to vcpu had
                 * been set in PIR before this function.
                 *
                 * Following cases will be reached in this block, and
                 * we always send a notification event in all cases as
                 * explained below.
                 *
                 * Case 1: vcpu keeps in non-root mode. Sending a
                 * notification event posts the interrupt to vcpu.
                 *
                 * Case 2: vcpu exits to root mode and is still
                 * runnable. PIR will be synced to vIRR before the
                 * next vcpu entry. Sending a notification event in
                 * this case has no effect, as vcpu is not in root
                 * mode.
                 *
                 * Case 3: vcpu exits to root mode and is blocked.
                 * vcpu_block() has already synced PIR to vIRR and
                 * never blocks vcpu if vIRR is not cleared. Therefore,
                 * a blocked vcpu here does not wait for any requested
                 * interrupts in PIR, and sending a notification event
                 * which has no effect is safe here.
                 */

                apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
                return true;
        }
#endif
        return false;
}